Design Lifecycle
Lint
Synthesis
0 data points
Timing Slack
—
Awaiting pipeline data
DRC Violations
—
Awaiting pipeline data
Avg Power
—
Awaiting pipeline data
Prop Delay
—
Awaiting pipeline data
Cell Composition
—Awaiting synthesis data
Chip Area
— Wires
—Console output appears here
bsa_ecore_pe
Logic Synthesis › No active pipeline — Idle
0s